Draw and explain the block diagram of the programmable peripheral interface (8255A). 

Draw and explain the block diagram of the programmable peripheral interface (8255A).


Data Bus Buffer :
  • This three-state bi-directional 8-bit buffer is used to interface the 8255 to the system data bus. 
  • Data is transmitted or received by the buffer upon execution of input or output instructions by the CPU. 
  • Control words and status information are also transferred through the data bus buffer. 

Group A and Group B Controls :
  • In  8255  I/O  port  are  divided  into  2  section  GA  &  GB. 
  • Group  A  consist  port  A  &  port  C  upper 
  • Group  B  consist  port  B  &  port  C  lower 
  • Each  group  is  programmed  through  software.
  • GA  &  GB  control  block  receives  command  from  the  R/W  control  logic  to  accept  bit  pattern  from  CPU. 
  • The  bit  pattern  given  by  consist  of  information.
  • To  control  the  operation  of  GA  &  GB.
  • The  mode  in  which  they  should  be  operated.  

Read / Write  control  logic :
  • this  block  accepts  input  from  system   control  bus  &   address  bus  performs  operations.
  • RD’  &  WR’  and  address  signal  used  are  A0  &  A1  and  CS’.
  • RD’  &  WR’  connected  to  IOR’  &  IOW’  or  MEMR’  &  MEMW’.
  • A0  &  A1  of  8085  are  directly  connected  to  address  line  A0  &  A1  of  8255.
  • Operation  is  enable /  disable  by  CS’  signal.  

Ports A, B, and C :
  • The 8255 contains three 8-bit ports (A, B, and C).
  • All can be configured to a wide variety of functional characteristics by the system software but each has its own special features or "personality" to further enhance the power and flexibility of the 8255.
  • Port A One 8-bit data output latch/buffer and one 8-bit data input latch.
  • Both "pull-up" and "pull-down" bus-hold devices are present on Port A.
  • Port B One 8-bit data input/output latch/buffer and one 8-bit data input buffer. Port C One 8-bit data output latch/buffer and one 8-bit data input buffer (no latch for input). This port can be divided into two 4-bit ports under the mode control.
  • Each 4-bit port contains a 4-bit latch and it can be used for the control signal output and status signal inputs in conjunction with ports A and B.